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PIC16LF1906-IPTQTP 数据表(PDF) 54 Page - Microchip Technology |
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PIC16LF1906-IPTQTP 数据表(HTML) 54 Page - Microchip Technology |
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54 / 288 page  PIC16LF1904/6/7 DS41569A-page 54 Preliminary 2011 Microchip Technology Inc. 5.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset conditions of these registers. TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE TABLE 5-4: RESET CONDITION FOR SPECIAL REGISTERS(2) STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 10 x1 1 Power-on Reset 0 0 1 1 10 x0 x Illegal, TO is set on POR 0 0 1 1 10 xx 0 Illegal, PD is set on POR 0 0 u 1 1u 01 1 Brown-out Reset u u 0 u uu u0 u WDT Reset u u u u uu u0 0 WDT Wake-up from Sleep u u u u uu u1 0 Interrupt Wake-up from Sleep u u u 0 uu uu u MCLR Reset during normal operation u u u 0 uu u1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u uu uu u Stack Overflow Reset (STVREN = 1) u 1 u u uu uu u Stack Underflow Reset (STVREN = 1) Condition Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 00-1 110x MCLR Reset during normal operation 0000h ---u uuuu uu-u 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-u 0uuu WDT Reset 0000h ---0 uuuu uu-0 uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-u uuuu Brown-out Reset 0000h ---1 1uuu 00-1 11u0 Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-u uuuu RESET Instruction Executed 0000h ---u uuuu uu-u u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-u uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as ‘0’. |
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