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PIC16LF1906-ISOSQTP 数据表(PDF) 76 Page - Microchip Technology |
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PIC16LF1906-ISOSQTP 数据表(HTML) 76 Page - Microchip Technology |
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76 / 288 page ![]() PIC16LF1904/6/7 DS41569A-page 76 Preliminary 2011 Microchip Technology Inc. 7.6.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 7-5. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 U-0 U-0 U-0 U-0 U-0 R/W-0/0 U-0 U-0 — — — — — LCDIF — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 LCDIF: LCD Module Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1-0 Unimplemented: Read as ‘0’ |
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