PIC16LF1906-ISOSQTP datasheet(89/288 Pages) MICROCHIP

89 / 288 page

 2011 Microchip Technology Inc.

Preliminary

DS41569A-page 89

PIC16LF1904/6/7

10.2.3

ERASING FLASH PROGRAM

MEMORY

While executing code, program memory can only be

erased by rows. To erase a row:

Load the PMADRH:PMADRL register pair with

any address within the row to be erased.

Clear the CFGS bit of the PMCON1 register.

Set the FREE and WREN bits of the PMCON1

Write 55h, then AAh, to PMCON2 (Flash

programming unlock sequence).

Set control bit WR of the PMCON1 register to

begin the erase operation.

See Example 10-2.

After the “BSF PMCON1,WR” instruction, the processor

requires two cycles to set up the erase operation. The

user must place two NOP instructions after the WR bit is

set. The processor will halt internal operations for the

typical 2 ms erase time. This is not Sleep mode as the

clocks and peripherals will continue to run. After the

erase cycle, the processor will resume operation with

the third instruction after the PMCON1 write instruction.

FIGURE 10-4:

FLASH PROGRAM

MEMORY ERASE

FLOWCHART

Disable Interrupts

(GIE = 0)

Start

Erase Operation

Select

Program or Configuration Memory

(CFGS)

Select Row Address

(PMADRH:PMADRL)

Select Erase Operation

(FREE = 1)

Enable Write/Erase Operation

(WREN = 1)

Unlock Sequence

(FIGURE x-x)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Erase Operation

CPU stalls while

Erase operation completes

(2 ms typical)

Figure 10-3

PIC16LF1906-ISOSQTP 数据表(PDF) 89 Page - Microchip Technology

PIC16LF1906-ISOSQTP 数据表(HTML) 89 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载