LP61L256C datasheet(9/11 Pages) AMICC

部件名	LP61L256C

功能描述	32K X 8 BIT HIGH SPEED CMOS SRAM

PDF	11 Pages

Scroll/Zoom	100%

制造商	AMICC [AMIC Technology]

网页	http://www.amictechnology.com

标志

9 / 11 page

LP61L256C Series

PRELIMINARY

(November, 2001, Version 0.0)

AMIC Technology, Inc.

AC Test Conditions

Input Pulse Levels

0V to 3.0V

Input Rise and Fall Time

2 ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Figures 1 and 2

+3.3V

I/O

351

Ω

317

Ω

5pF*

* Including scope and jig.

ZO=50

Ω

OUTPUT

RL=50

Ω

VT=1.5V

Figure 1. Output Load

Figure 2. Output Load for tCLZ, tOLZ,

tCHZ, tOHZ, tWHZ, and tOW

Data Retention Characteristics (TA = 0

°C to 70°C)

Symbol

Parameter

Min.

Max.

Unit

Conditions

VDR

VCC for Data Retention

3.6

≥ VCC - 0.2V

ICCDR

Data Retention Current

VCC = 2.0V

≥ VCC - 0.2V

VIN

≥ VCC - 0.2V or

VIN

≤ 0.2V

tCDR

Chip Disable to Data Retention

Time

See Retention Waveform

Operation Recovery Time

tRC*

tRC = Read Cycle Time

LP61L256C 数据表(PDF) 9 Page - AMIC Technology

LP61L256C 数据表(HTML) 9 Page - AMIC Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11

数据表下载