LP61L256C

Preliminary

32K X 8 BIT HIGH SPEED CMOS SRAM

PRELIMINARY

(November, 2001, Version 0.0)

1

AMIC Technology, Inc.

Features

n Single +3.3V power supply

n Access times: 12/15 ns (max.)

n Current: Operating: 120mA (max.)

Standby:

5mA (max.)

n Full static operation, no clock or refreshing required

n All inputs and outputs are directly TTL compatible

n Common I/O using three-state output

n Data retention voltage: 2V (min.)

n Available in 28-pin SOJ package

General Description

The LP61L256C is a high-speed, low-power 262,144-bit

static random access memory organized as 32,768

words by 8 bits and operates on a single 3.3V power

supply. It is built using high performance CMOS process.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

Minimum standby power is drawn by this device when

CE is at a high level, independent of the other input

levels.

Data retention is guaranteed at a power supply voltage

as low as 2V.

Pin Configurations

n SOJ

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

GND

CE

OE

A11

A9

A8

A13

WE

VCC

A10

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28