STM32F051K4 datasheet(87/104 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F051x

88/105

Doc ID 022265 Rev 3

Figure 26.

SPI timing diagram - slave mode and CPHA = 0

tsu(NSS)

(1)

NSS setup time

Slave mode

4Tpclk

th(NSS)

(1)

NSS hold time

Slave mode

2Tpclk + 10

tw(SCKH)

(1)

tw(SCKL)

(1)

SCK high and low time

Master mode, fPCLK = 36 MHz,

presc = 4

Tpclk/2 -2

Tpclk/2 + 1

tsu(MI)

(1)

tsu(SI)

(1)

Data input setup time

Master mode

Slave mode

th(MI)

(1)

Data input hold time

Master mode

th(SI)

(1)

Slave mode

ta(SO)

(1)(2)

Data output access time

Slave mode, fPCLK = 20 MHz

3Tpclk

tdis(SO)

(1)(3)

Data output disable time

Slave mode

tv(SO)

(1)

Data output valid time

Slave mode (after enable edge)

22.5

tv(MO)

(1)

Data output valid time

Master mode (after enable edge)

th(SO)

(1)

Data output hold time

Slave mode (after enable edge)

11.5

th(MO)

(1)

Master mode (after enable edge)

DuCy(SCK)

SPI slave input clock duty

cycle

Slave mode

Data based on characterization results, not tested in production.

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

Table 66.

SPI characteristics (continued)

Symbol

Parameter

Conditions

Min

Max

Unit

ai14134c

CPHA= 0

MOSI

INPUT

MISO

OUT P UT

CPHA= 0

MS B O UT

MSB IN

BI T6 OUT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BI T1 IN

NSS input

tSU(NSS)

tc(SCK)

th(NSS)

ta(SO)

tw(SCKH)

tw(SCKL)

tv(SO)

th(SO)

tr(SCK)

tf(SCK)

tdis(SO)

tsu(SI)

th(SI)

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