STM32F415RG datasheet(21/186 Pages) STMICROELECTRONICS

21 / 186 page

DocID022063 Rev 4

21/186

STM32F415xx, STM32F417xx

Description

Figure 6. Multi-AHB matrix

2.2.8

DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8

streams each. They are able to manage memory-to-memory, peripheral-to-memory and

memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,

support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is

needed when the controller reaches the end of the buffer. The two DMA controllers also

have a double buffering feature, which automates the use and switching of two memory

buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software

trigger on each stream. Configuration is made by software and transfer sizes between

source and destination are independent.

ARM

Cortex-M4

DMA1

DMA2

MAC

Ethernet

USB OTG

Bus matrix-S

ICODE

DCODE

Flash

memory

SRAM1

112 Kbyte

SRAM2

16 Kbyte

AHB1

peripherals

AHB2

FSMC

Static MemCtl

ai18490c

CCM data RAM

64-Kbyte

APB1

APB2

peripherals

STM32F415RG 数据表(PDF) 21 Page - STMicroelectronics

STM32F415RG 数据表(HTML) 21 Page - STMicroelectronics

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