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STM32F207VC 数据表(PDF) 125 Page - STMicroelectronics |
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STM32F207VC 数据表(HTML) 125 Page - STMicroelectronics |
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125 / 178 page  DocID15818 Rev 11 125/178 STM32F20xxx Electrical characteristics 177 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 53 or Figure 54, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 53. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. Figure 54. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. V REF+ STM32F V DDA V SSA/V REF- 1 µF // 10 nF 1 µF // 10 nF ai17535 (See note 1) (See note 1) VREF+/VDDA STM32F 1 µF // 10 nF VREF–/VSSA ai17536 (See note 1) (See note 1) |
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