SPC5643AF0MLU2 datasheet(113/138 Pages) FREESCALE

部件名	SPC5643AF0MLU2

功能描述	MPC5644A Microcontroller Data Sheet

PDF	138 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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113 / 138 page

MPC5644A Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

113

Figure 23. DSPI classic SPI timing — master, CPHA = 0

4 The actual minimum SCK cycle time is limited by pad performance.

5 For DSPI channels using LVDS output operation, up to 40 MHz SCK cycle time is supported. For non-LVDS output,

maximum SCK frequency is 20 MHz. Appropriate clock division must be applied.

6 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].

7 Timing met when pcssck = 3(01), and cssck =2 (0000).

8 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

9 Timing met when ASC = 2 (0000), and PASC = 3 (01).

10 Timing met when pcssck = 3.

11 Timing met when ASC = 3.

12 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.

Data

Last Data

First Data

Data

Last Data

SIN

SOUT

PCSx

SCK Output

(CPOL=0)

(CPOL=1)

Note: Refer to Table 48 for the numbers.

SPC5643AF0MLU2 数据表(PDF) 113 Page - Freescale Semiconductor, Inc