MPC8347ECVRALDB datasheet(18/99 Pages) FREESCALE

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

DDR and DDR2 SDRAM

Table 15 provides the DDR capacitance when GVDD(typ) = 2.5 V.

Table 16 provides the current draw characteristics for MVREF.

6.2

DDR and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.

6.2.1

DDR and DDR2 SDRAM Input AC Timing Specifications

Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.

Table 18 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5 V.

Table 15. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS

CIO

Delta input/output capacitance: DQ, DQS

CDIO

—0.5

Note:

1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

Table 16. Current Draw Characteristics for MVREF

Parameter/Condition

Symbol

Min

Max

Unit

Note

Current draw for MVREF

IMVREF

—500

μA1

Note:

1. The voltage regulator for MVREF must supply up to 500 μA current.

Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions with GVDD of 1.8 ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—MVREF – 0.25

—

AC input high voltage

VIH

MVREF + 0.25

—

Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions with GVDD of 2.5 ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—MVREF – 0.31

—

AC input high voltage

VIH

MVREF + 0.31

—

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