PIC16F882-I datasheet(36/328 Pages) MICROCHIP

36 / 328 page

PIC16F882/883/884/886/887

DS41291F-page 34

2.2.2.6

PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-6.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0

R/W-0

R-0

R/W-0

—

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6

ADIF: A/D Converter Interrupt Flag bit

= A/D conversion complete (must be cleared in software)

= A/D conversion has not completed or has not been started

bit 5

RCIF: EUSART Receive Interrupt Flag bit

= The EUSART receive buffer is full (cleared by reading RCREG)

= The EUSART receive buffer is not full

bit 4

TXIF: EUSART Transmit Interrupt Flag bit

= The EUSART transmit buffer is empty (cleared by writing to TXREG)

= The EUSART transmit buffer is full

bit 3

SSPIF: Master Synchronous Serial Port (MSSP) Interrupt Flag bit

= The MSSP interrupt condition has occurred, and must be cleared in software before returning from the

Interrupt Service Routine. The conditions that will set this bit are:

SPI

A transmission/reception has taken place

I2C Slave/Master

A transmission/reception has taken place

I2C Master

The initiated Start condition was completed by the MSSP module

The initiated Stop condition was completed by the MSSP module

The initiated restart condition was completed by the MSSP module

The initiated Acknowledge condition was completed by the MSSP module

A Start condition occurred while the MSSP module was idle (Multi-master system)

A Stop condition occurred while the MSSP module was idle (Multi-master system)

= No MSSP interrupt condition has occurred

bit 2

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare mode:

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 1

TMR2IF: Timer2 to PR2 Interrupt Flag bit

= A Timer2 to PR2 match occurred (must be cleared in software)

= No Timer2 to PR2 match occurred

bit 0

TMR1IF: Timer1 Overflow Interrupt Flag bit

= The TMR1 register overflowed (must be cleared in software)

= The TMR1 register did not overflow

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