AS5030 datasheet(4/44 Pages) AMSCO

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AS5030

Datasheet - Pin Assignm ents

4 Pin Assignments

Figure 2. Pin Assignments (Top View)

4.1 Pin Descriptions

Table 1. Pin Descriptions

Pin Number

Pin Name

Pin Type

Description

MagRngn

Digital output / tri-state

Push-Pull output. Is ‘HIGH’ when the magnetic field strength is too

weak, e.g. due to missing magnet

PROG

Supply pin

Programming voltage input. Must be left open in normal operation.

Maximum load = 20pF (except during programming)

VSS

Supply ground

T3_SINn

This pin is used for factory testing. For normal operation it must be left

unconnected. Inverse SIN (Sinn) output in SIN/COS output mode

T2_SIN

This pin is used for factory testing. For normal operation it must be left

unconnected. SIN output in SIN/COS mode

T1_COSn

This pin is used for factory testing. For normal operation it must be left

unconnected. Inverse COS (Cosn) output in SIN/COS mode

T0_COS

This pin is used for factory testing. For normal operation it must be left

unconnected. COS output in SIN/COS mode

Test pin. Connect to VSS or leave unconnected

Digital output

Digital output for 2-wire operation and Daisy Chain mode

CLK

Digital input /

Schmitt-Trigger

Clock Input of Synchronous Serial Interface; Schmitt-Trigger input

Chip Select for serial data transmission, active high; Schmitt-Trigger

input, external pull-down resistor (~50k

Ω) required in read-only mode

DIO

Bi-directional digital pin Data output / command input for digital serial interface

VDD

Supply pin

Positive supply voltage, 4.5V to 5.5V

Digital input

(standard CMOS; no

pull-up or pull-down)

Configuration input: Connect to VSS for normal operation,

connect to VDD to enable SIN-COS outputs. This pin is scanned at

power-on-reset and at wake-up from one of the Ultra-low Power Modes

Configuration input: Connect to VSS for 3-wire operation,

connect to VDD for 2-wire operation. This pin is scanned at power-on-

reset and at wake-up from one of the Ultra-low Power Modes

PWM

Digital output

Pulse Width Modulation output, 2µs pulse width per step

(2µs ~ 512µs)

PROG

VSS

test3

test2

test1

test0

MagRngn

CLK

DIO

VDD

PWM

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