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Revision 1.1

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AS8002

Data Sheet - D e t a i l e d D e s c r i p t i o n

7.10 Register Description

Table 9. 01h

Address:

01h

Control Register

Controls the power on and off of the internal blocks

Bit

Bit Name

Default

Access

Description

0

chip_en

0h

R/W

0: Chip in complete power off

1: Chip on

1

temp_sensor_en

0h

R/W

0: Temperature sensor disabled

1: Temperature sensor enabled

2

pga_curr_en

0h

R/W

0: Current channel PGA disabled

1: Current channel PGA enabled

3

pga_volt_en

0h

R/W

0: Voltage channel PGA disabled

1: Voltage channel PGA enabled

4

adcref_en

0h

R/W

0: Internal ADC reference voltage off

1: Internal ADC reference voltage on

Note:

This bit must be set to allow ADC measurements.

5

over_current_en

0h

R/W

0: Over current detector disabled

1: Over current detector enabled

6

over_current_channel

0h

R/W

0: Over current detector connected to inputs IOP_VOP and IOM_VOM

1: Over current detector connected to inputs V2P and V2M

Table 10. 02h

Address:

02h

PGA Gain Register

Controls the gain of the current and voltage channel PGAs

Bit

Bit Name

Default

Access

Description

4:0

pga_curr_gain

00h

R/W

Gain for current channel is given by the formula:

2*pga_curr_gain+2

(EQ 4)

7:6

pga_volt_gain

0h

R/W

Gain for voltage channel is given by the formula:

2*pga_volt_gain+2

(EQ 5)

Table 11. 03h

Address:

03h

Input Multiplexer Register

Controls the ADC and select the channel to be converted

Bit

Bit Name

Default

Access

Description

2:0

mux_sel

00h

R/W

Select the input to be converted:

0: Current channel PGA output

1: Voltage channel PGA output

2: V2P and V2M

3: AVDD and AVSS

4: IOP_VOP and IOM_VOM

5: V1P and V1M

6: Reserved

7: Reserved

4

adc_en

0h

R/W

Enable the ADC conversion that will start on the next SCSB falling edge