I2CSTAT datasheet(135/210 Pages) MICROCHIP

135 / 210 page

DS70139G-page 135

dsPIC30F2011/2012/3012/3013

17.8

Peripheral Module Disable (PMD)

Registers

The Peripheral Module Disable (PMD) registers

provide a method to disable a peripheral module by

stopping all clock sources supplied to that module.

When a peripheral is disabled via the appropriate PMD

control bit, the peripheral is in a minimum power

consumption state. The Control and Status registers

associated with the peripheral will also be disabled so

writes to those registers will have no effect and read

values will be invalid.

A peripheral module will only be enabled if both the

associated bit in the PMD register is cleared and the

peripheral is supported by the specific dsPIC DSC

variant. If the peripheral is present in the device, it is

enabled in the PMD register by default.

17.9

In-Circuit Debugger

When MPLAB® ICD 2 is selected as a Debugger, the

In-Circuit Debugging functionality is enabled. This

function allows simple debugging functions when used

with MPLAB IDE. When the device has this feature

enabled, some of the resources are not available for

general use. These resources include the first 80 bytes

of Data RAM and two I/O pins.

One of four pairs of Debug I/O pins may be selected by

the user using configuration options in MPLAB IDE.

These

pairs

are

named

EMUD/EMUC,

EMUD1/EMUC1,

EMUD2/EMUC2

and

EMUD3/EMUC3.

In each case, the selected EMUD pin is the

Emulation/Debug Data line, and the EMUC pin is the

Emulation/Debug Clock line. These pins will interface

to the MPLAB ICD 2 module available from Microchip.

The selected pair of Debug I/O pins is used by MPLAB

ICD 2 to send commands and receive responses, as

well as to send and receive data. To use the In-Circuit

Debugger function of the device, the design must

implement ICSP connections to MCLR, VDD, VSS,

PGC, PGD and the selected EMUDx/EMUCx pin pair.

This gives rise to two possibilities:

If EMUD/EMUC is selected as the Debug I/O pin

pair, then only a 5-pin interface is required, as

the EMUD and EMUC pin functions are multi-

plexed with the PGD and PGC pin functions in

all dsPIC30F devices.

EMUD1/EMUC1,

EMUD2/EMUC2

EMUD3/EMUC3 is selected as the Debug I/O

pin pair, then a 7-pin interface is required, as the

EMUDx/EMUCx pin functions (x = 1, 2 or 3) are

not multiplexed with the PGD and PGC pin

functions.

Note 1: If a PMD bit is set, the corresponding

module is disabled after a delay of 1

instruction cycle. Similarly, if a PMD bit is

cleared, the corresponding module is

enabled after a delay of 1 instruction

cycle (assuming the module Control reg-

isters are already configured to enable

module operation).

2: In dsPIC30F2011, dsPIC30F3012 and

dsPIC30F2012 devices, the U2MD bit is

readable and writable and will be read as

‘1’ when set.

I2CSTAT 数据表(PDF) 135 Page - Microchip Technology

I2CSTAT 数据表(HTML) 135 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载