AD5171

Rev. D | Page 17 of 24

Table 10. SDA Bits Definitions and Descriptions

Bit

Description

S

Start Condition.

P

Stop Condition.

A

Acknowledge.

AD0

X

Don’t Care.

T

OTP Programming Bit. Logic 1 programs the wiper position permanently.

D5, D4, D3, D2, D1, D0

Data Bits.

E1, E0

OTP Validation Bits:

0, 0 = Ready to Program.

0, 1 = Test Fuse Not Blown Successfully. For factory setup checking purpose only. Users should not see these

combinations.

1, 0 = Fatal Error. Do not retry. Discard the unit.

1, 1 = Programmed Successfully. No further adjustments are possible.

Write Bit Patterns

SDA

SCL

0

1

1

0

11

0 AD0 R/W

0

X

X

X

X

X

X

X

X

XD5

D4

D3

D2

D1

D0

91

91

9

STOP BY

MASTER

FRAME 1

DATA BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 1

SLAVE ADDRESS BYTE

START BY

MASTER

ACK. BY

AD5171

ACK. BY

AD5171

ACK. BY

AD5171

Figure 35. Writing to the RDAC Register

SDA

SCL

0

1

1

0

11

0 AD0 R/W

1X

X

X

X

X

X

X

X

X

D5

D4D3

D2D1

D0

91

91

9

STOP BY

MASTER

FRAME 1

DATA BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 1

SLAVE ADDRESS BYTE

START BY

MASTER

ACK. BY

AD5171

ACK. BY

AD5171

ACK. BY

AD5171

Figure 36. Activating One-Time Programming

Read Bit Pattern

SDA

SCL

0

1

1

0

11

0 AD0

E1

E0

D5

D4

D3

D2

D1

D0

91

9

R/W

STOP BY

MASTER

FRAME 2

RDAC REGISTER

FRAME 1

SLAVE ADDRESS BYTE

START BY

MASTER

NO ACK. BY

MASTER

ACK. BY

AD5171

Figure 37. Reading Data from RDAC Register

For users who prefer to use external controllers, the AD5171

connected to this bus as a slave device. The following section

Figure 35, Figure 36, and Figure 37).

The master initiates data transfer by establishing a start condition,

which is when SDA goes from high to low while SCL is high

(see Figure 35 and Figure 36). The following byte is the slave

address byte, which consists of the 6 MSBs as a slave address

address bit. Depending on the states of their AD0 bits, two

AD5171s can be addressed on the same bus (see Figure 38). The

last LSB is the R/W bit, which determines whether data is read

from, or written to, the slave device.

The slave address corresponding to the transmitted address bit

(this is termed the acknowledge bit). At this stage, all other

devices on the bus remain idle while the selected device waits

for data to be written to, or read from, its serial register.

The write operation contains one instruction byte more than

the read operation. The instruction byte in the write mode

follows the slave address byte. The MSB of the instruction byte

labeled T is the one-time programming bit. After acknowledging