AD5171

Rev. D | Page 20 of 24

For log taper adjustment, such as volume control, Figure 44

shows another way of resistance scaling. In this circuit, the

pseudo log taper characteristic. The wiper voltage is simply

I

WB

WA

WB

W

V

2

R

R

R

2

R

R

D

V

×

+

=

||

)

||

(

)

(

(6)

R1

B

A

R2

W

Figure 44. Resistor Scaling with Log Adjustment Characteristics

RESOLUTION ENHANCEMENT

The resolution can be doubled in the potentiometer mode of

operation by using three digital potentiometers. Borrowed from

the Analog Devices patented RDAC segmentation technique,

users can configure three AD5171s to double the resolution (see

Adjusting U1 and U2 together forms the coarse 6-bit adjustment,

and adjusting U3 alone forms the finer 6-bit adjustment. As a

result, the effective resolution becomes 12-bit.

U1

A1

B1

W1

U2

A2

B2

W3

W2

U3

A3

B3

COARSE

ADJUSTMENT

FINE

ADJUSTMENT

Figure 45. Doubling the Resolution

RDAC CIRCUIT SIMULATION MODEL

The internal parasitic capacitances and the external capacitive

loads dominate the ac characteristics of the digital potentiometers.

Configured as a potentiometer divider, the –3 dB bandwidth of

the AD5171 (5 kΩ resistor) measures 1.5 MHz at half scale.

Figure 14 to Figure 17 provide the large signal BODE plot

characteristics of the four available resistor versions: 5 kΩ,

10 kΩ, 50 kΩ, and 100 kΩ. A parasitic simulation model is

shown in Figure 46. Listing 1 provides a macro model net list

for the 10 kΩ device.

55pF

25pF

25pF

A

B

RDAC

10kΩ

W

Figure 46. Circuit Simulation Model for RDAC = 10 kΩ

Listing 1. Macro Model Net List for RDAC

.PARAM D=64, RDAC=10E3

*

.SUBCKT DPOT (A,W,B)

*

CA

A

0

25E-12

RWA

A

W

{(1-D/64)*RDAC+60}

CW

W

0

55E-12

RWB

W

B

{D/64*RDAC+60}

CB

B

0

25E-12

*

.ENDS DPOT