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OPA830TDBVREP 数据表(PDF) 3 Page - National Semiconductor (TI) |
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OPA830TDBVREP 数据表(HTML) 3 Page - National Semiconductor (TI) |
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3 / 36 page ![]() 1 2 3 5 4 Output −V S Noninverting Input +V S Inverting Input SLM Terminal Orientation/Package Marking SOT23−5 OPA830-EP www.ti.com SBOS655 – MARCH 2014 5 Terminal Configuration and Functions Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. OUT 1 O Amplifier Output -VS 2 I Negative Amplifier Power Supply Input +IN 3 I Non-inverting Amplifier Input -IN 4 I Inverting Amplifier Input +VS 5 I Positive Amplifier Power Supply Input 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Power Supply 12VDC V Internal Power Dissipation See Thermal Analysis Differential Input Voltage ±2.5 V Input Voltage Range (Single Supply) –0.5 +VS + 0.3 V Lead Temperature (soldering, 10s) 300 °C TJ Junction Temperature 150 °C (1) These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. 6.2 Handling Ratings MIN MAX UNIT Tstg Storage Temperature Range: D, DBV –65 125 °C Human Body Model (HBM)(2) 2000 V ESD Charge Device Model (CDM)(3) 1500 V Rating(1) Machine Model (MM) 200 V (1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device. (2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: OPA830-EP |
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