L9733

Serial peripheral interface (SPI)

Doc ID 11319 Rev 11

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5

Serial peripheral interface (SPI)

The L9733 has a serial peripheral interface consisting of Serial Clock (SCLK), Data Out

(DO), Data In (DI), and Chip Select (CS). All outputs will be controlled via the SPI. The input

pins CS, SCLK, and DI, thanks to VDO pin, have level input voltages allowing proper

operation from microcontrollers that are using 5.0 or 3.3 volts for their Vdd supply. The

design of the L9733 allows a "daisy-chaining" of multiple L9733's to further reduce the need

for controller pins.

5.1

Serial data output (DO)

This output pin is in a tri-state condition when CS is a logic '1'. When CS is a logic '0', this

pin transmits 16 bits of data from the fault register to the digital controller. After the first 16

bits of DO fault data are transmitted (after a CS transition from a logic '1' to a logic '0'), then

the DO output sequentially transmits the digital data that was just received (16 SCLK cycles

earlier) on the DI pin. The DO output continues to transmit the 16 SCLK delayed bit data

from the DI input until CS eventually transitions from a logic '0' to a logic '1'. DO data

changes state 10 nsec or later, after the falling edge of SCLK. The LSB is the first bit of the

byte transmitted on DO and the MSB is the last bit of the byte transmitted on DO, once CS

transitions from a logic '1' to a logic '0'.

5.2

Serial data input (DI)

This input takes data from the digital controller while CS is low. The L9733 accepts an 16 bit

byte to command the outputs on or off. The L9733 also serially wraps around the DI input

bits to the DO output after the DO output transmits its 16 fault flag bits. The LSB is the first

bit of each byte received on DI and the MSB is the last bit of each byte received on DI, once

CS transitions from a logic '1' to a logic '0'. The last 4 bits (b15-b12) of the first 16 bit byte

are used as key-word. The 4 bits (b11-b8) of the first 16 bits byte are used to select writing

mode between OUT8-1 status and diagnosis operating mode . The DI input has a nominal

100 k

 resistor connected from this pin to the VDO pin, which pulls this pin to VDO if an

open circuit condition occurs.

5.3

Chip select (CS)

This is the chip select input pin. On the falling edge of CS, the DO pin is released from tri-

state mode. While CS is low, register data are shifted in and shifted out the DI pin and DO

pin, respectively, on each subsequent SCLK. On the rising edge of CS, the DO pin is tri-

stated and the fault register is "Cleared" if a valid DI byte has been received. A valid DI byte

is defined as such:

–

a multiple of 16 bits was received.

–

a valid key-word was received

The fault data is not cleared unless all of the 2 previous conditions have been met. The CS

input has a nominal 100 k

 resistor connected from this pin to the VDO pin, which pulls this

pin to VDO if an open circuit condition occurs.