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STM8AF528ATAY 数据表(PDF) 13 Page - STMicroelectronics |
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STM8AF528ATAY 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 114 page  DocID14395 Rev 10 13/114 STM8AF52/62xx, STM8AF51/61xx Block diagram 113 4 Block diagram Figure 1. STM8A block diagram 1. Legend: ADC: Analog-to-digital converter beCAN: Controller area network BOR: Brownout reset I²C: Inter-integrated circuit multimaster interface IWDG: Independent window watchdog LINUART: Local interconnect network universal asynchronous receiver transmitter POR: Power on reset SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous asynchronous receiver transmitter Window WDG: Window watchdog XTAL 1-24 MHz RC int. 16 MHz RC int. 128 kHz STM8A CORE Debug/SWIM I 2C SPI USART LINUART 16-bit general purpose AWU timer Reset block Reset Clock controller Detector Clock to peripherals and core 10 Mbit/s LIN master Up to Window WDG IWDG Up to 128 Kbyte Up to 2 Kbytes Up to 6 Kbytes Boot ROM 10-bit ADC beCAN 9 CAPCOM Reset 400 Kbit/s 1 Mbit/s Master/slave Single wire automatic debug interf. SPI emul. channels high density program Flash 16-bit advanced control timer (TIM1) (TIM2, TIM3) 8-bit AR timer (TIM4) data EEPROM RAM Up to 16 channels resynchronization POR BOR |
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