STM8AF528ATAY datasheet(38/114 Pages) STMICROELECTRONICS

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Pinouts and pin description

STM8AF52/62xx, STM8AF51/61xx

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DocID14395 Rev 10

PI6

I/O X

X—

— O1

Port I6

——

PI7

I/O X

X—

— O1

Port I7

——

73 57 41 25 25 PD0/TIM3_CH2 I/O X

HS O3

Port D0

Timer 3 -

channel 2

TIM1_BKIN

[AFR3]/

CLK_CCO

[AFR2]

74 58 42 26 26

PD1/SWIM(4)

I/O X

XHS O4

Port D1

SWIM data

interface

—

75 59 43 27 27 PD2/TIM3_CH1 I/O X

HS O3

Port D2

Timer 3 -

channel 1

TIM2_CH3

[AFR1]

76 60 44 28 28 PD3/TIM2_CH2 I/O X

HS O3

Port D3

Timer 2 -

channel 2

ADC_ETR

[AFR0]

77 61 45 29 29

PD4/TIM2_CH1/

BEEP

I/O X

HS O3

Port D4

Timer 2 -

channel 1

BEEP

output

[AFR7]

78 62 46 30 30

PD5/

LINUART_TX

I/O X

— O1

Port D5

LINUART

data

transmit

—

79 63 47 31 31

PD6/

LINUART_RX

I/O X

— O1

Port D6

LINUART

data

receive

—

80 64 48 32 32

PD7/TLI(5)

I/O X

— O1

Port D7

Top level

interrupt

—

1. In Halt/Active-halt mode, this pin behaves as follows:

- The input/output path is disabled.

- If the HSE clock is used for wakeup, the internal weak pull-up is disabled.

- If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the

corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in

Halt/Active-halt mode.

2. SPI is not available in STM8AF5286UC, refer to Figure 7: STM8AF5286UC VFQFPN32 32-pin pinout for the pin names.

3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up and protection diode to VDD are

not implemented)

4. The PD1 pin is in input pull-up during the reset phase and after reset release.

5. If this pin is configured as interrupt pin, it will trigger the TLI.

Table 13. STM8A microcontroller family pin description (continued)

Pin number

Pin name

Input

Output

Main

function

(after

reset)

Default

alternate

function

Alternate

function

after remap

[option bit]

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