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Table 1: Control Functions

Control

Error Flags

Cycle

S1

S0

EDAC Function

Data UO

Checkword

SEF

DEF

WRITE

Low

Low

Generates Checkword

Input Data

Output Checkword

Low

Low

READ

Low

High

Read Data BCheckword

Input Data

Input Checkword

Low

Low

READ

High

High

Latch & Flag Error

Latch Data

Latch Checkword

Enabled

Enabled

READ

High

Low

Correct Data Word &

Output

Output Syndrome Bits

Enabled

Enabled

Generate Syndrome Bits

Corrected

Data

Table 2: Error Functions

Total Number of Errors

Error Flags

Data Correction

16-bit Data

6-bit Checkword

SEF

DEF

0

0

Low

Low

Not Applicable

1

0

High

Low

Correctlon

0

1

High

Low

Correction

1

1

High

High

Interrupt

2

0

High

High

Interrupt

0

2

High

High

Interrupt

ERROR DETECTION & CORRECTION

During a memory write cycle, six check bits (CBO-CB5)

are generated by eight-input parity generators using the data

bits defined in Table 3. During a memory read cycle, the 6-bit

checkword is retrieved along with the actual data.

Error detection is accomplished as the 6-bit checkword and

the 16-bit data word from memory are applied to internal parity

generators/checkers. If the parity of all six groupings of data

and check bits are correct, it is assumed that no error has

occurred and both error flags will be low. It should be noted

that the sense of two of the check bits, bits CBO and CB1, is

inverted to ensure that the gross-error condition of all lows and

all highs is detected.

If the parity of one or more of the check groups is incorrect,

an error has occurred and the proper error flag or flags will be

set high. Any single error in the 16bit data word will change the

sense of exactly three bits of the 6-bit checkword. Any single

error in the 6bit checkword changes the sense of only that one

bit. In either case, the single error flag will be set high while the

dual error flag will remain low.

Any two-bit error will change the sense of an even number

of check bits. The two-bit error is not correctable since the

parity tree can only identify singlebit errors. Both error flags are

set high when any two-bit error is detected.

Three or more simultaneous bit errors cause the EDAC to

transmit that no error, a correctable error, or an uncorrectable

error has occurred and hence produce erroneous results in all

three cases.

Error correction is accomplished by identifying the bad bit

and inverting it. Identification of the erroneous bit is achieved

by comparing the 16-bit word and 6-bit checkword from

memory with the new checkword with one (checkword error)

or three (data word error) inverted bits.

As the corrected word is made available on the data word l/

O port, the checkword l/O port presents a 6-bit syndrome error

code. This syndrome code can be used to identify the

corrupted bit in memory (see Table 4. overleaf).