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3D7702Z-O2 数据表(PDF) 4 Page - Data Delay Devices, Inc.

部件名 3D7702Z-O2
功能描述  MONOLITHIC GATED DELAY LINE OSCILLATOR (SERIES 3D7702)
PDF  5 Pages
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制造商  DATADELAY [Data Delay Devices, Inc.]
网页  http://www.datadelay.com
标志 DATADELAY - Data Delay Devices, Inc.

3D7702Z-O2 数据表(HTML) 4 Page - Data Delay Devices, Inc.

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3D7702
APPLICATION NOTES (CONT’D)
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7702 oscillator utilizes novel
and innovative compensation circuitry to
minimize the frequency variations induced by
fluctuations in power supply and/or temperature.
The thermal coefficient is reduced to 250 PPM/C,
which is equivalent to a variation, over the -40C
to 85C operating range, of
±1.5% from the room-
temperature frequency setting. The power supply
coefficient is reduced, over the 4.75V to 5.25V
operating range, to
±0.5% of the frequency
setting at the nominal 5.0VDC power supply.
These specifications hold for the lower
frequencies only. For higher dash numbers, the
variations will be slightly greater, as noted in
Table 1. It is essential that the power supply
pin be adequately bypassed and filtered. In
addition, the power bus should be of as low
an impedance construction as possible.
Power planes are preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
DC Supply Voltage
VDD
-0.3
7.0
V
Input Pin Voltage
VIN
-0.3
VDD+0.3
V
Input Pin Current
IIN
-1.0
1.0
mA
25C
Storage Temperature
TSTRG
-55
150
C
Lead Temperature
TLEAD
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Static Supply Current*
IDD
3.5
5.5
mA
High Level Input Voltage
VIH
2.0
V
Low Level Input Voltage
VIL
0.8
V
High Level Input Current
IIH
1.0
µA
VIH = VDD
Low Level Input Current
IIL
1.0
µA
VIL = 0V
High Level Output
Current
IOH
-35.0
-4.0
mA
VDD = 4.75V
VOH = 2.4V
Low Level Output Current
IOL
4.0
15.0
mA
VDD = 4.75V
VOL = 0.4V
Output Rise & Fall Time
TR & TF
2.0
2.5
ns
CLD = 5 pf
*IDD(Dynamic) = 2 * CLD * VDD * F
Input Capacitance = 10 pf typical
where: CLD = Average capacitance load/output (pf)
Output Load Capacitance (CLD) = 25 pf max
F = Device frequency (GHz)
Doc #06024
DATA DELAY DEVICES, INC.
4
12/5/2006
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com



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