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LP38853 数据表(PDF) 14 Page - Texas Instruments |
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LP38853 数据表(HTML) 14 Page - Texas Instruments |
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14 / 27 page ![]() LP38853 SNVS335C – DECEMBER 2006 – REVISED SEPTEMBER 2011 www.ti.com In any case, the output voltage cannot be ensured until both VIN and VBIAS are within the range of specified operating values. If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommended for this diode clamp. REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass element is not driven, there will not be any reverse current flow through the pass element during a reverse voltage event. The gate of the pass element is not driven when VBIAS is below the UVLO threshold, or when the Enable pin is held low. When VBIAS is above the UVLO threshold, and the Enable pin is above the VEN(ON) threshold, the control circuitry is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass element to the full VBIAS potential when the output voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin , limited only by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up 1000 µF in this manner will not damage the device as the current will rapidly decay. However, continuous reverse current should be avoided. SOFT-START The LP38853 incorporates a Soft-Start function that reduces the start-up current surge into the output capacitor (COUT) by allowing VOUT to rise slowly to the final value. This is accomplished by controlling VREF at the SS pin. The soft-start timing capacitor (CSS) is internally held to ground until both VBIAS rises above the Under-Voltage Lock-Out threshold (ULVO) and the Enable pin is higher than the VEN(ON) threshold. VREF will rise at an RC rate defined by the internal resistance of the SS pin (rSS), and the external capacitor connected to the SS pin. This allows the output voltage to rise in a controlled manner until steady-state regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is sufficiently close to the final steady-state value. During the soft-start time the output current can rise to the built-in current limit. Soft-Start Time = CSS × rSS × 5 (7) Since the VOUT rise will be exponential, not linear, the in-rush current will peak during the first time constant (τ), and VOUT will require four additional time constants (4τ) to reach the final value (5τ) . After achieving normal operation, should either VBIAS fall below the ULVO threshold, or the Enable pin fall below the VEN(OFF) threshold, the device output will be disabled and the Soft-Start capacitor (CSS) discharge circuit will become active. The CSS discharge circuit will remain active until VBIAS falls to 500 mV (typical). When VBIAS falls below 500 mV (typical), the CSS discharge circuit will cease to function due to a lack of sufficient biasing to the control circuitry. Since VREF appears on the SS pin, any leakage through CSS will cause VREF to fall, and thus affect VOUT. A leakage of 50 nA (about 10 M Ω) through CSS will cause VOUT to be approximately 0.1% lower than nominal, while a leakage of 500 nA (about 1 M Ω) will cause VOUT to be approximately 1% lower than nominal. Typical ceramic capacitors will have a factor of 10X difference in leakage between 25°C and 85°C, so the maximum ambient temperature must be included in the capacitor selection process. Typical CSS values will be in the range of 1 nF to 100 nF, providing typical Soft-Start times in the range of 70 μs to 7 ms (5 τ). Values less than 1 nF can be used, but the Soft-Start effect will be minimal. Values larger than 100 nF will provide soft-start, but may not be fully discharged if VBIAS falls from the UVLVO threshold to less than 500 mV in less than 100 µs. Figure 32 shows the relationship between the COUT value and a typical CSS value. 14 Submit Documentation Feedback Copyright © 2006–2011, Texas Instruments Incorporated Product Folder Links: LP38853 |
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