MB90P641APFV datasheet(3/96 Pages) FUJITSU

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MB90640A Series

s PRODUCT LINEUP

MB90641A

MB90P641A

Classification

Mask ROM

One-time PROM

ROM size

64 Kbytes

RAM size

2 Kbytes

CPU functions

The number of instructions: 340

Instruction bit length:

8/16 bits

Instruction length:

1 to 7 bytes

Data bit length:

1/4/8/16/32 bits

Minimum execution time:

58.8 ns at 4.25 MHz (PLL multiplier = 4)

Interrupt processing time:

941 ns at 17 MHz (minimum)

Ports

8/16-bit data bus, multiplexed mode: 56 ports (max)

8-bit non-multiplexed mode:

48 ports (max)

Single-chip mode:

75 ports (max)

Packages

FPT-100P-M05

FPT-100P-M06

UART0, 1 (SCI)

Two internal UARTs

Full-duplex, double-buffered

Selectable clock synchronous or asynchronous operation

Built-in dedicated baud rate generator

8/16-bit PPG

× 8-bit PPG outputs

(1 channel PPG output in 16-bit mode)

16-bit reload timer

16-bit reload timer operation (selectable toggle output, one-shot output)

(Selectable count clock: 0.125

µs, 0.5 µs, or 2.0 µs for a 16 MHz machine cycle)

Selectable event count function, 5 internal channels

Chip select function

8 outputs

DTP/external interrupts

8 inputs

External interrupt mode

(Interrupts can be generated from four different types of request signal)

PLL function

Selectable multiplier: 1/2/3/4

(Set a multiplier that does not exceed the assured operation frequency range.)

External bus terminal

control circuit

Multiplex and non-multiplex between the adress pin and the data pin is selectable.

Part number

Item

MB90P641APFV 数据表(PDF) 3 Page - fujitsu semiconductor

MB90P641APFV 数据表(HTML) 3 Page - fujitsu semiconductor

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