The junction temperature of the device can be estimated

from the equation below:

(

)

=

+ θ

×

J_MAX

A_MAX

JA

LOSS

TT

P

If the application has a thermal management system that

ensures that the exposed pad of the device is maintained

heatsinks, then the junction temperature of the device can

be estimated at any given maximum ambient temperature

from the equation below:

(

)

=

+ θ

×

J_MAX

EP_MAX

JC

LOSS

TT

P

PCB Layout Guidelines

All connections carrying pulsed currents must be very

short and as wide as possible. The inductance of these

connections must be kept to an absolute minimum due to

the high di/dt of the currents. Since inductance of a current

carrying loop is proportional to the area enclosed by the

loop, if the loop area is made very small, inductance is

reduced. Additionally, small-current loop areas reduce

radiated EMI.

A ceramic input filter capacitor should be placed close

inductance effects as possible and gives the IC a cleaner

should be placed close to the pin to reduce effects of trace

impedance.

When routing the circuitry around the IC, the analog

small-signal ground and the power ground for switching

currents must be kept separate. They should be connected

together at a point where switching activity is at a

capacitor. This helps keep the analog ground quiet.

The ground plane should be kept continuous/unbroken

as far as possible. No trace carrying high switching

current should be placed directly over any ground plane

discontinuity.

PCB layout also affects the thermal performance of the

design. A number of thermal vias that connect to a large

ground plane should be provided under the exposed pad

of the part, for efficient heat dissipation.

For a sample layout that ensures first pass success,

refer to the MAX17543 evaluation kit layout available at

www.maximintegrated.com.

MAX17543

4.5V–42V, 2.5A, High-Efficiency,

Synchronous Step-Down DC-DC Converter

with Internal Compensation

www.maximintegrated.com

Maxim Integrated │ 16