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A7985ATR 数据表(PDF) 24 Page - STMicroelectronics |
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A7985ATR 数据表(HTML) 24 Page - STMicroelectronics |
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24 / 44 page  Application information A7985A 24/44 DocID023128 Rev 5 The suggested maximum system bandwidth is equal to the switching frequency divided by 3.5 (FSW/3.5), so lower than 100 kHz if the FSW is set higher than 500 kHz. For example, with VOUT = 5 V, VIN = 24 V, IO = 2 A, L = 22 H, COUT = 22 F, and ESR < 1 m , the Type III compensation network is: Equation 29 In Figure 12 the module and phase of the open loop gain is shown. The bandwidth is about 32 kHz and the phase margin is 51 °. Figure 12. Open loop gain Bode diagram with ceramic output capacitor R1 4.99k = R2 680 = R3 270 = R4 1.1k = C3 4.7nF = C4 47nF = C5 1pF = |
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