STAC9708 datasheet(21/56 Pages) ETC

21 / 56 page

SigmaTel, Inc.

Preliminary

STAC9708/11

10/02/98

3.1.2.2 Slot 2: Status Data Port

The status data port delivers 16-bit control register read data.

Bit (19:4)

Control Register Read Data

(Stuffed with 0's if tagged "invalid")

Bit (3 :0)

RESERVED

(Stuffed with 0's)

If Slot 2 is tagged "invalid" by STAC9708/11, then the entire slot will be stuffed with 0's.

3.1.2.3 Slot 3: PCM Record Left Channel

Audio input frame slot 3 is the left channel output of STAC9708/11 input MUX, post-ADC.

STAC9708/11 ADCs are implemented to support 18-bit resolution.

STAC9708/11 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit

positions with 0's to fill out its 20-bit time slot.

3.1.2.4 Slot 4: PCM Record Right Channel

Audio input frame slot 4 is the right channel output of STAC9708/11 input MUX, post-ADC.

STAC9708/11 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit

positions with 0's to fill out its 20-bit time slot.

3.1.2.5 Slots 5-12: Reserved

Audio input frame slots 5-12 are not used by the STAC97908/11 and are always stuffed with

0's.

3.2 AC-Link Low Power Mode

The STAC9708/11 AC-Link can be placed in the low power mode by programming register 26h to the

appropriate value. Both BIT_CLK and SDATA_IN will be brought to, and held at a logic low voltage

level. The AC'97 controller can wake up the STAC9708/11 by providing the appropriate reset signals.

STAC9708 数据表(PDF) 21 Page - List of Unclassifed Manufacturers