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STAC9708 数据表(PDF) 16 Page - List of Unclassifed Manufacturers |
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STAC9708 数据表(HTML) 16 Page - List of Unclassifed Manufacturers |
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16 / 56 page ![]() SigmaTel, Inc. Preliminary STAC9708/11 16 10/02/98 the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. Figure 7. Start of an Audio Output Frame SYNC BIT_CLK SDATA_OUT STAC9708 samples first SDATA_OUT bit of frame here STAC9708 samples SYNC assertion here valid Frame slot1 slot2 End of previous audio frame SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions stuffed with 0’s by the AC'97 controller. When mono audio sample streams are sent from the AC'97 controller, it is necessary that BOTH left and right sample stream time slots be filled with the same data. 3.1.1.1 Slot 1: Command Address Port The command port is used to control features, and monitor status (see Audio Input Frame Slots 1 and 2) of the STAC9708/11 functions including, but not limited to, mixer settings, and power management (refer to the control register section of this specification). The control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid. Audio output frame slot 1 communicates control register address, and write/read command information to the STAC9708/11. Command Address Port bit assignments: Bit (19) Read/Write command (1= read, 0=write) Bit (18:12) Control Register Index (64 16-bit locations, addressed on even byte boundaries) Bit (11:0) Reserved (Stuffed with 0's) The first bit (MSB) sampled by STAC9708/11 indicates whether the current control transaction is a read or a write operation. The following 7 bit positions communicate the targeted control register address. The trailing 12 bit positions within the slot are reserved and must he stuffed with 0's by the AC'97 controller. |
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