STAC9708 datasheet(37/56 Pages) ETC

37 / 56 page

SigmaTel, Inc.

Preliminary

STAC9708/11

10/02/98

AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14

and 13) and place a non-zero value (01, 10, or 11) into the Codec ID field (Slot 0, bits 1 and 0).

As a Secondary Codec, the STAC9708/11 will disregard the Command Address and Command Data (Slot 0, bits

14 and 13) tag bits when it sees a 2-bit Codec ID value (Slot 0, bits 1 and 0) that matches its configuration. In a

sense the Secondary Codec ID field functions as an alternative Valid Command Address (for Secondary reads and

writes) and Command Data (for Secondary writes) tag indicator.

Secondary Codecs must monitor the Frame Valid bit, and ignore the frame (regardless of the state of the

Secondary Codec ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid bit for a frame

with a secondary register access, even if no other bits in the output tag slot except the Secondary Codec ID bits

are set.

This method is designed to be backward compatible with existing AC'97 controllers and Codecs. There is no

change to output Slot 1 or 2 definitions.

Table 22. Secondary Codec Register Access Slot 0 Bit Definitions

Output Tag Slot (16-bits)

Bit

Description

Frame Valid

Slot 1 Valid Command Address bit

(†Primary Codec only)

Slot 2 Valid Command Data bit

(†Primary Codec only)

12-3

Slot 3-12 Valid bits as defined by AC'97

Reserved

(Set to “0”)

†1-0

2-bit Codec ID field

(00 reserved for Primary; 01, 10, 11 indicate Secondary)

† New definitions for Secondary Codec Register Access

7. TESTABILITY

The STAC9708/11 has two test modes. One is for ATE in-circuit test and the other is restricted for SigmaTel’s

internal use. STAC9708/11 enters the ATE in circuit test mode if SDATA_OUT is sampled high at the trailing

edge of RESET#.

Once in the ATE test mode, the digital AC-Link outputs (BIT_CLK and SDATA_IN) are

driven to a high impedance state. This allows ATE in-circuit testing of the AC'97 controller. This case will

never occur during standard operating conditions. Once either of the two test modes have been entered, the

STAC9704/7 must be issued another rest with all AC-link signals held low to return to the normal operating

mode.

STAC9708 数据表(PDF) 37 Page - List of Unclassifed Manufacturers

STAC9708 数据表(HTML) 37 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载