13

ICS1522

24-Pin SOIC Package

ICS XXXX M

Example:

Package Type

M=SOIC

Device Type (consists of 3 or 4 digit numbers)

ICS=Standard Device

Prefix

Ordering Information

ICS1522M

Pixel-by-Pixel Adjustment of

To understand the operation of the pixel-by-pixel phase

adjust-ment feature, imagine that the modulus of the on-

chip divider is equivalent to the graphics system overall

divide. Also, imagine that the overflow of the internal

divider occurs at the same time as the overflow of the

graphics system line counter. Initial synchronization is

accomplished by switching from the external feedback

source (graphics system HSYNC) to the internal feedback.

Let us assume that we are now using the internal divider.

Now, imagine that the programmed value of the divider

(really a prescaler) is increased by one for a single pass-

through that prescaler (think of this as “swallowing” a

feedback pulse). We will lose exactly one CLK period of

phase in the feedback path. The VCO will speed up

momentarily to compensate for that, and re-lock the loop.

In doing so, the graphics system will receive exactly one

extra CLK cycle, advancing the phase of the graphics

system HSYNC by one CLK period relative to the reference

HSYNC. In a similar fashion, we can decrease the

programmed value of the prescaler (“adding” a pulse) to

retard the phase of the graphics system. Additionally, sub-

pixel phase adjustment is provided through varying the

voltage at the FINE input pin.

ICS reserves the right to make changes in the device data identified in this publication

without further notice. ICS advises its customers to obtain the latest version of all

device data to verify that any information being relied upon by the customer is current

and accurate.