6

ICS1522

REG#

BIT(S)

BIT REF.

DESCRIPTION

4

3-5

PFD (0;2)

Phase Frequency Detector Gain

4

6

PDEN

Phase Frequency Detector Enable

(Default=1) 0=PFD Disable; 1=PFD Enable

4

7

INT_FLT

Loop Filter Select (Default=1)

0=External Loop Filter (IPUMP & VVCO active)

1=Internal Loop Filter

4

8

INT_VCO

VCO Select (Default=1)

0=External VCO (EXTVCO active)

1=Internal VCO

4

9

CLK_SEL

Feedback Divider Clock Input Select (Default=0)

0=VCO; 1=OUT1

4

1 0

RESERVED

Must be set to one.

5

0

FBK_SEL

Feedback Select (Default=1)

0=External Feedback (EXTFBK active)

1=Internal Feedback An active external feedback signal at EXTFBK

is necessary to synchronously switch to internal.

5

1

FBK_POL

External Feedback Polarity (Default=0)

0=Positive Edge; 1=Negative Edge

5

2

ADD

Addition of 1 VCO Cycle (Default=0)

Toggle (0 to 1 to 0) to add 1 VCO cycle.

5

3

SWLW

Removal of 1 VCO Cycle (Default=0)

Toggle (0 to 1 to 0) to remove 1 VCO cycle.

PFD(2)

PFD(1)

PFD(0)

PFD GAIN

FINE PHASE

ADJ.

0

0

0

.2344uA/2

3ns/V

0

0

1

.9375uA/2

3ns/V

0

1

0

3.750uA/2

3ns/V

0

1

1

15.00uA/2

3ns/V

1

0

0

1.875uA/2

6ns/V

1

0

1

7.500uA/2

6ns/V

1

1

0

30.00uA/2

1.5ns/V

1

1

1

120.0uA/2

.375ns/V