IR81 Interrupt Enables

Bit 7 - Master Interrupt Enable (MIE)

In the zero state, this bit prevents the IRQ pin from

going active (high) regardless of the state of any of the

individual interrupt sources. It is cleared to zero by

MCR. A zero in this bit does not prevent an individual

interrupt source from being active in the STATUS reg-

ister. This allows interrupts to be masked while allow-

ing their status to be polled.

Bit 6 - reserved

Bit 5 - Sample Rate Interrupt Enable (SRIE)

Bit 4 - FIFO Overflow/Underflow Interrupt

Enable (FOUIE)

Bit 3 - Power-down Mode Change Interrupt

Enable (PMCIE)

Bit 2 - reserved

Bit 1 - Record FIFO Interrupt Enable (RFIE)

Bit 0 - Play FIFO Interrupt Enable (PFIE)

Each of these bits individually enables, one, or disables,

zero, their respective interrupt sources from being ac-

tive in the STATUS register. In addition, there will be

no IRQ generated if MIE is one when an individual

enable bit is zero. The state of this bit does not affect

the source of these interrupts in any way, and they may

be polled for activity in the appropriate register for each

interrupt type. These bits are all cleared to zero by

MCR.

IR83 Status

This register is the same as the direct access status register,

except that it can be read in COMPANION mode.

Sample Rate Generator Registers

IR84 Sample Rate Low 8 bits (SRL)

Bits 7:0 - Sample Rate Bits 7:0

IR85 Sample Rate High 4 bits (SRH)

Bits 3:0 - Sample Rate Bits 11:8

Together, these two registers define the record and

playback sample rate. Based on the crystal frequency

FXtal, and a 12 bit value SR (the concatenation of the

two registers), the sample rate will be:

Sample Rate = FXtal * SR / 524288

These registers are not initialized by any of the reset

mechanisms. Note that the Sample Rate Counter should

always be stopped via SRCS bit 0 when these two

registers are changed.

IR86 Sample Rate Control/Status (SRCS)

Bits 7:2 - reserved

Bit 1 - Sample Rate Interrupt (SRIRQ) - Read Only

This is set by the hardware whenever the sample rate

counter overflows, indicating that a new sample is

being input or generated. This bit is cleared by any of

the following actions:

- Master Chip Reset

- Sample Rate Run = 0 (SRR bit 0)

- a write to STATUS with bit 5 = 1

- any write to SRCS

Bit 0 - Sample Rate Run (SRR)

This bit resets the Sample Rate Counter, the SRIRQ bit,

and shuts down the sampling and playback pro-cesses

when written to a zero. When written to a one, the

sample rate generator runs at the programmed rate.

SRR is internally synchronized to the master clock to

provide clean starts and stops of the counter. MCR

clears this bit.

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