FIFO Control/Status Registers

IR8C FIFO Enable/Status (FES)

Bit 0 - FIFO Enable (FE)

This bit holds the FIFO in a reset state when low, and

enables the FIFO to operate when high. This bit is reset

by MCR. This bit, when low, also resets all FIFO related

conditions (see the following bits) and prevents DMA

start requests from being issued. It does not reset the

FIFO IRQ Mode register.

Bit 1 - FIFO Overflow (read only)

This bit is set when a FIFO shift in command is gener-

ated (by either DMA, I/O, or the DSP) with the FIFO

full, and indicates an error condition. This bit will cause

the FOUIRQ bit to go active, generating an IRQ if

enabled. This bit is reset by writing to STATUS with bit

4 = 1, and re-enabled by writing to STATUS with bit 4

= 0. FE low also resets this bit.

Bit 2 - FIFO Underflow (read only)

This bit is set when a FIFO shift out command is

generated (by either DMA, I/O, or the DSP) with the

FIFO empty, and indicates an error condition. This bit

will cause the FOUIRQ bit to go active, generating an

IRQ if enabled. This bit is reset by writing to STATUS

with bit 4 = 1, and re-enabled by writing to STATUS

with bit 4 = 0. FE low also resets this bit.

Bit 3 - FIFO 25% Full (read only)

This bit goes high after 4 words (or 8 bytes) have been

loaded into the FIFO, and low again when 13 words (or

26 bytes) may be loaded into the FIFO. There is no

interrupt associated with this bit directly.

Bit 4 - FIFO 50% Full (read only)

This bit goes high after 8 words (or 16 bytes) have been

loaded into the FIFO, and low again when 9 words (or

18 bytes) may be loaded into the FIFO. There is no

interrupt associated with this bit directly.

Bit 5 - FIFO 75% Full (read only)

This bit goes high after 12 words (or 24 bytes) have

been loaded into the FIFO, and low again when 5 words

(or 10 bytes) may be loaded into the FIFO. There is no

interrupt associated with this bit directly.

Bit 6 - FIFO DIR (read only)

This bit goes high when a single word (or two bytes)

may be written to the FIFO. There is no interrupt

associated with this bit directly. Note that this bit resets

to a one because when the FIFO is reset it is forced to

be empty, and hence is ready to accept data.

Bit 7 - FIFO DOR (read only)

This bit goes high when a single word (or two bytes)

may be read from the FIFO. There is no interrupt

associated with this bit directly.

IR8D FIFO IRQ Mode

This register must never be written to when the FIFO is enabled.

Invalid interrupts and DMA requests could be generated as a

result.

Bits 7:4 - reserved

Bit 3 - FIFO IRQ Enable (FIE)

This bit enables the various FIFO capacity thresholds

to generate interrupts (as PLAYIRQ) when one. When

zero, this bit prevents FIFO capacity IRQ generation

when operating in DMA mode, which only needs

TCIRQ.

Bits 2:0 - FIFO Ready IRQ Mode Selection

This field defines FIFO utilization for both DMA and

I/O mode data transfers. In I/O mode, it is used to

generate interrupts (FRDYIRQ) when the FIFO capac-

ity reaches a predefined point. For DMA transfers, it

signals the DMA logic to request a transfer at those

same predefined points. By programming the DMA

Burst Count appropriately, the FIFO may be easily kept

near the desired capacity.

The following table describes the selections available:

Bits

2:0

IRQ/DRQ

Source

Notes

000

DIR

Ready to take 1 word from HOST

001

EMPTY 75%

Ready to take 13 words from

HOST

010

EMPTY 50%

Ready to take 9 words from HOST

011

EMPTY 25%

Ready to take 5 words from HOST

100

DOR

Ready to provide 1 word to DSP

101

FULL 25%

Ready to provide 4 words to DSP

110

FULL 50%

Ready to provide 8 words to DSP

111

FULL 75%

Ready to provide 12 words to DSP

Note that for byte transfers (DMA16=0), the numbers listed

above should be doubled.

This must be programmed before the FIFO is enabled. It may

be changed while the FIFO is enabled, if necessary. This

register is cleared by MCR, but not by FE low.

ICS2002

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