ICS2002 datasheet(19/21 Pages) ICST

19 / 21 page

IRA1 DAC De-glitcher Control

Bits 7:3 - Volume bits 7:3 (read only)

Bit 2 - DAC Enable Bit (read only, for test)

Bits 1:0 - DAC De-glitch Width

Code

Notes

De-glitcher disabled

Minimum de-glitch width

Nominal de-glitch width

Maximum de-glitch width

This value is determined by the clock rate at which the

chip is run. ICS will provide the proper value for an

application. This register is also used for test purposes.

This register is not initialized in any way and should be

programmed before muting is removed.

IRA2 reserved

IRA3 reserved

ADC and Analog Control Registers

IRA4 ADC Control

Bits 7:3 - reserved

Bit 2 - ADC Test Mode

This bit is for factory testing use only, and must always

be programmed to zero by an application. It is reset to

zero by a zero in ADCRUN, and hence takes two writes

of $05 to this register to activate for safety.

Bit 1 - reserved

Bit 0 - ADC Run

When written to a one, this bit enables the ADC hard-

ware to run. Note that the ADC Timing Control register

should be programmed appropriately first. Also note

that the DSP must be running (and programmed prop-

erly) for the conversion results to be retrieved. The

Sample Rate Generator determines the rate at which the

conversion data is loaded into the Record FIFO.

This bit is cleared to zero by MCR.

Note that this bit, when 0, shuts down the successive

approximation logic, the dynamic comparators and

various logic functions. When the ADC is not being

used, disabling it via this bit reduces background noise

in the playback section and power consumption, and

thus is recommended.

IRA5 Analog Volume/Mute

Bits 7:5 - reserved

Bits 4:1 - Analog Volume

These bits set the analog output level, in 1.5dB steps.

All bits one gives 0dB attenuation of the DAC output

signal, and all bits zero gives full attenuation. These bits

are unaffected by any reset mechanism.

Bit 0 - Audio Enable

This bit disconnects the audio output of the output

buffer amp and sets the BUFOUT pin to the nominal

bias voltage when cleared to zero. When set to one, it

passes the output of the output buffer amp to the

BUFOUT pin.

The main function of this bit is to prevent sudden DC

offset changes on the BUFOUT pin when entering and

leaving power-down mode. By proper software proce-

dure, noiseless transitions can be made.

This bit is cleared to zero by MCR.

IRA6 ADC Timing Control

This register is used to control the ADC internal opera-

tion timing.

Bits 7:4 - Comparator Timing Control

These bits control the time of comparator input switch-

ing. Bits 7:5 are the count, and bit 4 is 0 for half cycle

and 1 full cycle delays.

Bits 3:1 - Cycle Timing Control

These bits control the number of clocks used for each

step of the successive approximation process. For the

full 64 step DSP cycle, the value of these bits should be

7. For a 40 step cycle, the value should be 4.

Bit 0 - reserved

ICS2002

ICS2002 数据表(PDF) 19 Page - Integrated Circuit Systems

ICS2002 数据表(HTML) 19 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

数据表下载