ICS2008B

16

ICS2008B Rev D 4/05/05

Programming

The ICS2008B is a SMPTE time code input/output device

with a UART which can be used as a MIDI UART or transport

control UART. All of the time critical functions to read and gen-

erate time code are performed by the chip’s hardware, but all of

the intelligence for processing time codes and generating the

time code values are performed via an external processor. This

makes the ICS2008B flexible enough for a broad range of ap-

plications without making the processing requirements on the

host system too great.

Indirect Register Access

Indirect registers are accessed via the SMPTE2 (address) and

SMPTE3 (data) registers. To read an indirect register, the pro-

gram must first write its address to SMPTE2. Then the data is

read from SMPTE3. Writing to an indirect register is similar.

First, the address is written to SMPTE2. Then the data is writ-

ten to SMPTE3.

In order to minimize the number of accesses required to read

or write a block of registers, an auto-increment function is

provided. If the MSB of SMPTE2 is written to a one with the

address, the address is incremented after each read or write

access to SMPTE3. For example, if one wants to read the LTC

Read registers, IR0 to IR7, SMPTE2 is written to a 80h. Then

read SMPTE3 eight times. The first byte read is from IR0 fol-

lowed by IR1, etc.

Interrupt Processing

Interrupts can be generated from five sources, LTC receiver,

LTC generator, video line count, timer and UART. The inter-

rupt status of the first four interrupts, LRI, LXI, VLI and TMI

are in the SMPTE0 register. After this register is read, all four

interrupts are cleared. It is, therefore, necessary to save the

state of the interrupt status and process all active interrupts.

The UART interrupt status is in the UART0 register. The re-

ceive interrupt is cleared by reading the receive data register,

UART1. The transmit interrupt is cleared by writing data to

the transmit data register, UART1.

Reading LTC

When LTC data is received, it is placed into a temporary

buffer and transferred into the LTC read register (IR0 to IR7)

when the last bit of LTC data has been received. It should be

noted that the data is transferred before the SYNC pattern has

been received. Once the data is in the LTC receive buffer, the

LRI bit is set to one in the SMPTE0 register. If the LRIEN bit

(SMPTE0) is set to a one, an interrupt will be generated. The

interrupt is cleared when the SMPTE0 register is read. The

data in the LTC receive buffer remains valid until the next

LTC frame has been completely received.

LTC input data is available in the LTC Read registers after the

last LTC data bit has been received. It is not necessary to wait

for the LTC SYNC pattern to be complete. When LTC read

data is available the LRI bit in SMPTE0 is set to one. If

LRIEN is also set to one, an interrupt is generated. LRI and

the interrupt are cleared by reading SMPTE0. Data will re-

main valid until the last LTC data bit of the next frame has

been received.

The SMPTE1 register contains two status bits which indicate

whether LTC data is being received and if so which direction.

LTCLOCK is set to one when the LTC receiver has received a

valid LTC SYNC pattern and data is still coming in.

CODEDIR indicates the direction of the LTC SYNC pattern.

This is useful to tell whether a tape with LTC is shuttling for-

wards or backwards.

Generating LTC

The LTC generator transfers data from the LTC Write regis-

ters (IR8 to IRF) to the output buffer when the LTC generator

is enabled; LTCEN is set to one. Data transfers for subsequent

LTC frames occur eight bit times before the end of the LTC

frame being output. Remember that a LTC frame ends with a

16 bit SYNC pattern. The LXI interrupt bit in SMPTE0 is set

to one when LTC Write register data is transferred to the out-

put buffer.

A typical program for generating LTC output would first

setup the LTC control registers and the LTC bit time registers.

Then time code data would be written to the LTC Write regis-

ter. Once this setup is done the LTC output would be enabled

by setting LTCEN to a one. LTC output starts when a LTC

SYNC is received. The LTC SYNC source is selected as part

of the setup. While the LTC generator is waiting for SYNC,

the data in the LTC Write register is transferred to the output

buffer. When the transfer is complete the LXI status but is set

to a one. The data for the next LTC output frame can then be

loaded. The LXI status bit will be set to a one after the data

transfer at the end of the first LTC output frame. At this point

the LTC Write register is ready to receive data for a third LTC

output frame.