2

ICS9159-06

Preliminary Product Preview

Pin Descriptions

28-Pin 300-mil SOIC

Pin Configuration

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

8, 26

VDD

PWR

Power for logic, CPU and fixed frequency output buffers.

1X1

IN

XTAL or external reference frequency input. This input includes XTAL load

capacitance and feedback bias for a 0.5 - 20 MHz XTAL.**

2

X2

OUT

XTAL output which includes XTAL load capacitance.**

3, 11, 23

GND

PWR

Ground for logic, CPU and fixed frequency output buffers.

6, 7, 9

CPU(0:2)

OUT

Processor clock outputs which are a multiple of the input reference frequency as

shown in the table.

4, 5

FS(0:1)

IN

Frequency multiplier select pins. See table. These inputs have internal pull-up

devices.

20

VDDB

PWR

Power for BUS output buffers.

15, 16, 18 19,

21, 22

BUS(0:5)

OUT

Bus clock outputs are fixed at 33.3 or 16.7 MHz.*

24, 25, 27, 28

REF(0:3)

OUT

REF is a buffered copy of the crystal oscillator or reference input clock,

nominally 14.31818 MHz.*

10

ECPU

OUT

Early processor clock output which is the same frequency as CPU(0:2). This clock

leads CPU(0:2) by 3-6nS.

12

DOZE#

IN

Reduces CPU, ECPU and BUS clock outputs as shown in the functionality table

when at a logic low level.

13, 14

STP0#, STP1#

IN

Synchronously stops the CPU, ECPU and BUS clocks per the description in the

functionality table. Can also be used to tristate all outputs when the DOZE pin is

low.

17

GNDB

PWR

This ground return path is brought on separately to permit separating the noise

impulses from high output buffers from affecting sensitive internal circuitry.***

*

Assuming 14.31818 MHz input clock or crystal.

** Device provides 18pF load for crystal load capacitance at each pin.

*** Ground for bus clock buffers.