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ICS9159-06 数据表(PDF) 4 Page - Integrated Circuit Systems

部件名 ICS9159-06
功能描述  Frequency Generator and Buffer for Pentium Systems
PDF  7 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS9159-06 数据表(HTML) 4 Page - Integrated Circuit Systems

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ICS9159-06
Preliminary Product Preview
Electrical Characteristics at 3.3V
VDD = 3.1 – 3.7 V, TA = 0 – 70
°C
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
AC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rise Time
1
Tr1
20pF load, 0.8 to 2.0V, CPU & BUS
-
0.9
1.5
ns
Fall Time1
Tf1
20pF load, 2.0 to 0.8V, CPU & BUS
-
0.8
1.4
ns
Rise Time
1
Tr2
20pF load, 20% to 80%, CPU & BUS
-
1.5
2.5
ns
Fall Time
1
Tf2
20pF load, 80% to 20%, CPU & BUS
-
1.4
2.4
ns
Duty Cycle
1
Dt
20pF load; @VOUT=1.4V
40
50
60
%
Jitter, One Sigma
1
Tj1s
CPU; ECPU
Load=20pF;
FOUT >25 MHz
-60
150
ps
Jitter, Absolute
1
Tjab
CPU; ECPU
Load=20pF,
FOUT >25 MHz
-350
-
350
ps
Jitter, One Sigma1
Tj1s
BUS(0:2); REF(0:3); CPU
25 MHz;
Load=20pF; Comp. to the period
-0.7
2.0
%
Jitter, Absolute
1
Tjab
BUS(0:2); REF(0:3); CPU
25 MHz;
Load=20pF;
Comp. to the period
-3.0
-
3.0
%
Input Frequency
1
Fi
0.5 14.318 20 MHz Logic Input
Capacitance 1 CIN Logic input pins
-5
-
pF
Crystal Oscillator Capacitance1
CINX
X1, X2 pins
-
18
-
pF
Power-on Time1
ton
From VDD=1.6V to 1 st crossing of
66.6 MHz VDD supply ramp < 40ms
-2.5
4.5
ms
Frequency Settling Time
1
ts
From 1 st crossing of acquisition to
<1% settling
-2.0
4.0
ms
Clock Skew Window
1
Tsk1
CPU to CPU;
Load=20pF; @1.4V
-150
250
ps
Clock Skew Window
1
Tsk2
BUS to BUS and REF to REF;
Load=20pF; @1.4V
-300
500
ps
Clock Skew Window
1
Tsk3
ECPU to CPU(0:2);
Load=20pF; @1.4V
3.0
5.0
6.0
ns



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