IDT71342LA55J datasheet(8/13 Pages) IDT

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IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

6.05

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

W CONTROLLED TIMING(1, 5, 8)

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

CE CONTROLLED TIMING(1, 5)

NOTES:

1. R/

W or CE must be High during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of either

CE or SEM = VIL and R/W = VIL.

3. tWR is measured from the earlier of

CE or R/W going High to the end-of-write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the

CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (

CE or R/W) is asserted last.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output

Test Load (Figure 2).

8. If

OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to

be placed on the bus for the required tDW. If

OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be

as short as the specified tWP.

9. To access RAM,

CE =VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

2721 drw 11

tWC

ADDRESS

DATAIN

CE or SEM

tDW

tWR

tDH

tEW

tAS

tAW

(9)

(6)

(2)

(3)

CE or SEM

2721 drw 10

tAW

tAS

tWR

tDW

DATAIN

ADDRESS

tWC

tWP

tDH

DATAOUT

tWZ

(4)

tOW

tHZ

tLZ

tHZ

(9)

(6)

(7)

(2)

(3)

(7)

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