6.05

11

IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

TABLE I — NON-CONTENTION READ/WRITE CONTROL

Left or Right Port

(1)

R/

W

W

W

W

W

CE

CE

CE

CE

CE

SEM

SEM

SEM

SEM

SEM

OE

OE

OE

OE

OE

Function

X

H

H

X

Z

Port Disabled and in Power Down Mode

H

H

L

L

Data in Semaphore Flag Output on Port

X

X

X

H

Z

Output Disabled

u

H

L

X

Port Data Bit D0 Written Into Semaphore Flag

H

L

H

L

Data in Memory Output on Port

L

L

H

X

Data on Port Written Into Memory

X

L

L

X

—

Not Allowed

2721 tbl 13

NOTE:

"H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-impedance, and "

u" = Low-to-High transition.

processor writes a zero in the left port at a free semaphore

location. On a subsequent read, the processor will verify that

it has written successfully to that location and will assume

control over the resource in question. Meanwhile, if a processor

on the right side attempts to write a zero to the same semaphore

flag it will fail, as will be verified by the fact that a one will be

read from that semaphore on the right side during a subsequent

read. Had a sequence of READ/WRITE been used instead,

system contention problems could have occurred during the

gap between the read and write cycles.

It is important to note that a failed semaphore request must

be followed by either repeated reads or by writing a one into

the same location. The reason for this is easily understood by

looking at the simple logic diagram of the semaphore flag in

Figure 3.

Two semaphore request latches feed into a

semaphore flag. Whichever latch is first to present a zero to

the semaphore flag will force its side of the semaphore flag low

and the other side high. This condition will continue until a one

is written to the same semaphore request latch. Should the

other side’s semaphore request latch have been written to a

zero in the meantime, the semaphore flag will now stay low

until its semaphore request latch is written to a one. From this

it is easy to understand that, if a semaphore is requested and

the processor which requested it no longer needs the resource,

the entire can hang up until a one is written into that semaphore

request latch.

The critical case of semaphore timing is when both sides

request a single token by attempting to write a zero into it at

the same time. The semaphore logic is specially designed to

resolve this problem. If simultaneous requests are made, the

logic guarantees that only one side receives the token. If one

side is earlier than the other in making the request, the first

Function

Status

No Action

1

1

Semaphore free

Left Port Writes “0” to Semaphore

0

1

Left port has semaphore token

Right Port Writes “0” to Semaphore

0

1

No change. Right side has no write access to semaphore

Left Port Writes “1” to Semaphore

1

0

Right port obtains semaphore token

Left Port Writes “0” to Semaphore

1

0

No change. Left side has no write access to semaphore

Right Port Writes “1” to Semaphore

0

1

Left port obtains semaphore token

Left Port Writes “1” to Semaphore

1

1

Semaphore free

Right Port Writes “0” to Semaphore

1

0

Right port has semaphore token

Right Port Writes “1” to Semaphore

1

1

Semaphore free

Left Port Writes “0” to Semaphore

0

1

Left port has semaphore token

Left Port Writes “1” to Semaphore

1

1

Semaphore free

2721 tbl 14

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.