376 datasheet(34/95 Pages) INTEL

34 / 95 page

376 EMBEDDED PROCESSOR

phases ‘‘phase one’’ and ‘‘phase two’’ Each CLK2

period is a phase of the internal clock Figure 42

illustrates the relationship If desired the phase of

the internal processor clock can be synchronized to

a known phase by ensuring the falling edge of the

RESET signal meets the applicable setup and hold

times t25 and t26

DATA BUS (D15–D0)

These three-state bidirectional signals provide the

general purpose data path between the 80376 and

other devices The data bus outputs are active HIGH

and will float during bus hold acknowledge Data bus

reads require that read-data setup and hold times

t21 and t22 be met relative to CLK2 for correct oper-

ation

ADDRESS BUS (BHE BLE A23–A1)

These three-state outputs provide physical memory

addresses or IO port addresses A23–A16 are LOW

during IO transfers except for IO transfers auto-

matically generated by coprocessor instructions

During coprocessor IO transfers A22–A16 are driv-

en LOW and A23 is driven HIGH so that this ad-

dress line can be used by external logic to generate

the coprocessor select signal Thus the IO address

driven by the 80376 for coprocessor commands is

8000F8H and the IO address driven by the 80376

processor for coprocessor data is 8000FCH or

8000FEH

The address bus is capable of addressing 16 Mbytes

of physical memory space (000000H through

0FFFFFFH) and 64 Kbytes of IO address space

(000000H through 00FFFFH) for programmed IO

The address bus is active HIGH and will float during

bus hold acknowledge

The Byte Enable outputs BHE and BLE directly indi-

cate which bytes of the 16-bit data bus are involved

with the current transfer BHE applies to D15–D8

and BLE applies to D7–D0 If both BHE and BLE are

asserted then 16 bits of data are being transferred

See Table 41 for a complete decoding of these sig-

nals The byte enables are active LOW and will float

during bus hold acknowledge

Table 41 Byte Enable Definitions

BHE

BLE

Function

Word Transfer

Byte Transfer on Upper Byte of the Data Bus D15–D8

Byte Transfer on Lower Byte of the Data Bus D7–D0

Never Occurs

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