376 datasheet(39/95 Pages) INTEL

39 / 95 page

376 EMBEDDED PROCESSOR

Table 44 Pin State (Bus Idle) during RESET

Pin Name

Signal Level during RESET

ADS

D15–D0

Float

BHE BLE

A23–A1

MIO

LOCK

HLDA

42 Bus Transfer Mechanism

All data transfers occur as a result of one or more

bus cycles Logical data operands of byte and word

lengths may be transferred without restrictions on

physical address alignment Any byte boundary may

be used although two physical bus cycles are per-

formed as required for unaligned operand transfers

The 80376 processor address signals are designed

to simplify external system hardware BHE and BLE

provide linear selects for the two bytes of the 16-bit

data bus

Byte Enable outputs BHE and BLE are asserted

when their associated data bus bytes are involved

with the present bus cycle as listed in Table 45

Table 45 Byte Enables and Associated

Data and Operand Bytes

Byte Enable

Associated Data Bus Signals

BHE

D15–D8 (Byte 1Most Significant)

BLE

D7–D0 (Byte 0Least Significant)

Each bus cycle is composed of at least two bus

states Each bus state requires one processor clock

period Additional bus states added to a single bus

cycle are called wait states See Bus Functional

Description

for additional information

43 Memory and IO Spaces

Bus cycles may access physical memory space or

IO space Peripheral devices in the system may ei-

ther be memory-mapped or IO-mapped or both

As shown in Figure 43 physical memory addresses

range from 000000H to 0FFFFFFH (16 Mbytes) and

addresses

from

000000H

00FFFFH

(64 Kbytes) Note the IO addresses used by the

automatic IO cycles for coprocessor communica-

tion are 8000F8H to 8000FFH beyond the address

range of programmed IO to allow easy generation

of a coprocessor chip select signal using the A23

and MIO signals

OPERAND ALIGNMENT

With the flexibility of memory addressing on the

80376 it is possible to transfer a logical operand

that spans more than one physical Dword or word of

memory or IO Examples are 32-bit Dword or 16-bit

word operands beginning at addresses not evenly

divisible by 2

Operand alignment and size dictate when multiple

bus cycles are required Table 46 describes the

transfer cycles generated for all combinations of log-

ical operand lengths and alignment

Table 46 Transfer Bus Cycles

for Bytes Words and Dwords

Byte-Length of Logical Operand

Physical Byte

Address in

Memory

(Low-Order

Bits)

Transfer

hw mw

Cycles

Key

b e byte transfer

w e word transfer

l e low-order portion

m e mid-order portion

x e don’t care

h e high-order portion

376 数据表(PDF) 39 Page - Intel Corporation

376 数据表(HTML) 39 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

数据表下载