80960CF-30 datasheet(27/62 Pages) INTEL

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SPECIAL ENVIRONMENT 80960CF-30 -25 -16

AC Characteristics

80960CF-25

(80960CF-25 only under the conditions described in Section 42 Operating Conditions and Section 451

AC Test Conditions

) (Continued)

Symbol

Parameter

Min

Max

Units

Notes

RELATIVE OUTPUT TIMINGS(97)

TAVSH1

A312 Valid to ADS Rising

T b 4T a 4ns

TAVSH2

BE30 WR SUP DC

DMA DACK30 Valid to ADS Rising

T b 6T a 6ns

TAVEL1

A312 Valid to DEN Falling

T b 4T a 4ns

TAVEL2

BE30 WR SUP INST

DMA DACK30 Valid to DEN Falling

T b 6T a 6ns

TNLQV

WAIT Falling to Output Data Valid

6ns

TDVNH

Output Data Valid to WAIT Rising

N T b 6N T a 6

(4)

TNLNH

WAIT Falling to WAIT Rising

N T g 4

(4)

TNHQX

Output Data Hold after WAIT Rising

(N a 1)

T b 6(N a 1)

T a 6

(5)

TEHTV

DTR Hold after DEN High

T2 b 6

(6)

TTVEL

DTR Valid to DEN Falling

T2 b 4

T2 a 4

(7)

RELATIVE INPUT TIMINGS(7)

TIS5

RESET Input Setup (2x Clock Mode

(14)

TIH5

RESET Input Hold (2x Clock Mode)

(14)

TIS6

DREQ30 Input Setup

(8)

TIH6

DREQ30 Input Hold

(8)

TIS7

XINT70 NMI Input Setup

(8)

TIH7

XINT70 NMI Input Hold

(8)

TIS8

RESET Input Setup (1x Clock Mode)

(15)

TIH8

RESET Input Hold (1x Clock Mode)

T4 a 1

(15)

NOTES

(1) See Section 452 AC Timing Waveforms for waveforms and definitions

(2) See Figure 22 for capacitive derating information for output delays and hold times

(3) See Figure 23 for capacitive derating information for rise and fall times

(4) Where N is the number of NRAD NRDD NWAD orNWDD wait states that are programmed in the Bus Controller Region

Table When there are no wait states in an access WAIT never goes active

(5) N e Number of wait states inserted with READY

(6) Output Data andor DTR may be driven indefinitely following a cycle if there is no subsequent bus activity

(7) See Notes 1 2 and 3

(8) Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in

order to be recognized and for proper operation However to guarantee recognition of the input at a particular edge of

PCLK21 the setup times shown must be met Asynchronous inputs must be active for at least two consecutive PCLK21

rising edges to be seen by the processor

(9) These specifications are guaranteed by the processor

(10) These specifications must be met by the system for proper operation of the processor

(11) This timing is dependent upon the loading of PCLK21 Use the derating curves of Section 453 to adjust the timing for

PCLK21 loading

(12) In the 1-x input clock mode the maximum input clock period is limited to 125 ns while the processor is operating When

the processor is in reset the input clock may stop even in 1-x mode

(13) When in the 1-x input clock mode these specifications assume a stable input clock with a period variation of less than

01% between adjacent cycles

(14) In 2x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation

However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup and

hold times to the falling edge of the CLKIN (See Figure 28a)

(15) In 1x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation

However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must be deasserted

while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN (See Figure 28b)

80960CF-30 数据表(PDF) 27 Page - Intel Corporation

80960CF-30 数据表(HTML) 27 Page - Intel Corporation

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