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80960CF-30 数据表(PDF) 39 Page - Intel Corporation |
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80960CF-30 数据表(HTML) 39 Page - Intel Corporation |
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39 / 62 page ![]() SPECIAL ENVIRONMENT 80960CF-30 -25 -16 271328 – 24 NOTE Case 1 and Case 2 show two possible polarities of PCLK21 Figure 22a Clock Synchronization in the 2x Clock Mode 271328 – 25 NOTE In 1x clock mode the RESET pin is actually sampled on the falling edge of 2XCLK 2XCLK is an internal signal generat- ed by the PLL and is not available on an external pin Therefore RESET is specified relative to the rising edge of CLKIN The RESET pin is sampled when PCLK is high Figure 22b Clock Synchronization in the 1x Clock Mode 39 |
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