80960SA datasheet(13/39 Pages) INTEL

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80960SA

LOCK

I/O

O.D.

BUS LOCK prevents bus masters from gaining control of the bus during

Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert

LOCK.

At the start of a RMW operation, the processor examines the LOCK pin. If the pin is

already asserted, the processor waits until it is not asserted. If the pin is not

asserted, the processor asserts LOCK during the Ta cycle of the read transaction.

The processor deasserts LOCK in the Ta cycle of the write transaction. While LOCK

is asserted, a bus agent can perform a normal read or write but not a RMW

operation. The processor also asserts LOCK during interrupt-acknowledge transac-

tions.

Do not leave LOCK unconnected. It must be pulled high for the processor to

function properly.

ONCE MODE: The LOCK pin is sampled during reset. If it is asserted LOW at the

end of reset, all outputs will be three-stated until the part is reset again. ONCE

mode is used in conjunction with an in-circuit emulator.

BE1:0

T.S.

BYTE ENABLE LINES specify which data bytes (up to two) on the bus take part in

the current bus cycle. BE1 corresponds to AD15:8; BE0 corresponds to AD7:1, D0.

The byte enable lines are asserted appropriately during each data cycle.

INITIALIZATION FAILURE indicates that the processor has failed to initialize

correctly. The failure state is indicated by a combination of BLAST asserted and

BE1:0 not asserted. This condition occurs after RESET is deasserted and before

the first bus transaction begins. FAIL is asserted while the processor performs a

self-test. If the self-test completes successfully, FAIL is deasserted. The processor

then performs a zero checksum on the first eight words of memory, If it fails, FAIL is

asserted for a second time and remains asserted; if it passes, system initialization

continues and FAIL remains deasserted.

HOLD

HOLD indicates a request from an external bus master to acquire the bus. When

the processor receives HOLD and grants bus control to another master, it floats its

three-state bus lines, then asserts HLDA and enters the Th state. When HOLD is

deasserted, the processor deasserts HLDA and enters the Ti or Ta state.

HLDA

T.S.

HOLD ACKNOWLEDGE notifies an external bus master that the processor has

relinquished control of the bus. This signal is always driven. At reset it is driven

LOW.

BLAST/FAIL

T.S.

BURST LAST indicates the last data cycle (Td) of a burst access. It is asserted low

during the last Td and associated with Tw cycles in a burst access.

INITIALIZATION FAILURE indicates that the processor has failed to initialize

correctly. The failure state is indicated by a combination of BLAST asserted and

BE1:0 not asserted. This condition occurs after RESET is deasserted and before

the first bus transaction begins. FAIL is asserted while the processor performs a

self-test. If the self-test completes successfully, FAIL is deasserted. The processor

then performs a zero checksum on the first eight words of memory, If it fails, FAIL is

asserted for a second time and remains asserted; if it passes, system initialization

continues and FAIL remains deasserted.

Table 3. 80960SA Pin Description: Bus Signals (Sheet 2 of 2)

NAME

TYPE

DESCRIPTION

I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state

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