17

80960SA

Table 7. 80960SA AC Characteristics (16 MHz)

Symbol

Parameter

Min

Max

Units

Notes

Input Clock

Processor Clock Period (CLK2)

31.25

125

ns

Processor Clock Low Time (CLK2)

8

ns

=

Processor Clock High Time

(CLK2)

8

ns

=

Processor Clock Fall Time (CLK2)

10

ns

Processor Clock Rise Time (CLK2)

10

ns

Synchronous Outputs

Output Valid Delay

2

25

ns

AS Output Valid Delay

2

21

ns

ALE Width

ns

ALE Output Valid Delay

2

22

ns

Output Float Delay

2

20

ns

(2)

Synchronous Inputs

Input Setup 1

10

ns

Input Hold

2

ns

Input Setup 2

13

ns

Setup to ALE Inactive

10

ns

Hold after ALE Inactive

8

ns

RESET Hold

3

ns

(3)

RESET Setup

5

ns

(3)

RESET Width

1281

ns

41 CLK2 Periods Minimum

NOTES:

1. Processor clock (CLK2) rise time and fall time are not tested.

no longer than the valid delay.

3. Meeting RESET setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asyn-

chronous reset, synchronizing the clock can be accomplished by using AS.