6-9

2.4

-

-

V

Three-State Disabled Output

-3

-

-

µA

-

-

3

µA

Output Short Circuit Current,

4.5

6

-

mA

Output Short Circuit Current,

9.0

16

-

mA

NOTES:

1. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the

DGND, being careful to avoid ground loops.

will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful,

during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated tem-

50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply volt-

age of 4.950V over temperature variations, initial tolerance and loading.

3. With V+ = 6V, the digital logic interfaces are no longer TTL compatible.

4. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion

process.

5. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse

width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see

Timing Diagrams).

6. CLK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately.

7. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span

Electrical Specifications

(Notes 1, 7) (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Timing Waveforms

FIGURE 1. THREE-STATE CIRCUITS AND WAVEFORMS

10K

V+

RD

CS

DATA

OUTPUT

RD

2.4V

90%

50%

10%

0.8V

DATA

OUTPUTS

GND

90%

10K

V+

RD

CS

DATA

OUTPUT

V+

RD

2.4V

90%

50%

10%

0.8V

DATA

OUTPUTS

V+

10%

ADC0802, ADC0803, ADC0804