6-16

Driving the Data Bus

This CMOS A/D, like MOS microprocessors and memories,

will require a bus driver when the total capacitance of the

data bus gets large. Other circuItry, which is tied to the data

bus, will add to the total capacitive loading, even in three-

state (high-impedance mode). Back plane busing also

greatly adds to the stray capacitance of the data bus.

There are some alternatives available to the designer to han-

dle this problem. Basically, the capacitive loading of the data

bus slows down the response time, even though DC specifi-

cations are still met. For systems operating with a relatively

slow CPU clock frequency, more time is available in which to

establish proper logic levels on the bus and therefore higher

capacitive loads can be driven (see Typical Performance

Curves).

At higher CPU clock frequencies time can be extended for

I/O reads (and/or writes) by inserting wait states (8080) or

using clock-extending circuits (6800).

Finally, if time is short and capacitive loading is high,

external bus drivers must be used. These can be three-state

buffers (low power Schottky is recommended, such as the

74LS240 series) or special higher-drive-current products

which are designed as bus drivers. High-current bipolar bus

drivers with PNP inputs are recommended.

Power Supplies

Noise spikes on the V+ supply line can cause conversion

errors as the comparator will respond to this noise. A

low-inductance tantalum filter capacitor should be used

close to the converter V+ pin, and values of 1

µF or greater

are recommended. If an unregulated voltage is available in

the system, a separate 5V voltage regulator for the converter

(and other analog circuitry) will greatly reduce digital noise

on the V+ supply. An lCL7663 can be used to regulate such

a supply from an input as low as 5.2V.

Wiring and Hook-Up Precautions

Standard digital wire-wrap sockets are not satisfactory for

breadboarding with this A/D converter. Sockets on PC

boards can be used. All logic signal wires and leads should

be grouped and kept as far away as possible from the analog

signal leads. Exposed leads to the analog inputs can cause

undesired digital noise and hum pickup; therefore, shielded

leads may be necessary in many applications.

A single-point analog ground should be used which is separate

from the logic ground points. The power supply bypass capaci-

tor and the self-clockIng capacitor (if used) should both be

log input filter capacitors, or input signal shielding should be

returned to the analog ground point. A test for proper grounding

is to measure the zero error of the A/D converter. Zero errors in

layout and wiring (see Zero Error for measurement). Further

information can be found in Application Note AN018.

Testing the A/D Converter

There are many degrees of complexity associated with testing

an A/D converter. One of the simplest tests is to apply a

known analog input voltage to the converter and use LEDs to

display the resulting digital output code as shown in Figure 18.

with 2.560V and a V+ supply voltage of 5.12V should be

used. This provides an LSB value of 20mV.

If a full scale adjustment is to be made, an analog input volt-

put code is just changing from 1111 1110 to 1111 1111. This

The digital-output LED display can be decoded by dividing the 8

bits into 2 hex characters, one with the 4 most-significant bits

(MS) and one with the 4 least-significant bits (LS). The output is

then interpreted as a sum of fractions times the full scale voltage:

.

For example, for an output LED display of 1011 0110, the

MS character is hex B (decimal 11) and the LS character is

hex (and decimal) 6, so:

.

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

ADC0802 - ADC0804

WR

RD

CS

INTR

CLK IN

DGND

AGND

CLK R

V+

10K

10

µF

+

DATA

START

ANALOG

INPUTS

150pF

OUTPUTS

N.O.

MSB

LSB

FIGURE 17. FREE-RUNNING CONNECTION

V

OUT

MS

16

---------

LS

256

----------

+



 5.12

()V

=

START

DGND

2.560V

AGND

10

µF

150pF

N.O.

0.1

µF

0.1

µF

TANTALUM

5.120V

5V

1.3k

Ω LEDs

(8)

(8)

MSB

LSB

10k

Ω

+

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

ADC0802-

ADC0804

FIGURE 18. BASIC TESTER FOR THE A/D

V

OUT

11

16

------

6

256

----------

+



 5.12

()

3.64V

==

ADC0802, ADC0803, ADC0804