4-44

Absolute Maximum Ratings

Thermal Information

CDP1853/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V

CDP1853C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . .

±10mA

Thermal Resistance (Typical)

SBDIP Package . . . . . . . . . . . . . . . . . .

85

22

Device Dissipation Per Output Transistor

(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW

Lead Temperature (During Soldering)

At distance 1/16

±1/32 In. (1.59 ± 0.79mm)

Timing Diagrams

FIGURE 2A. N - INPUTS TO OUTPUTS DELAY TIME

FIGURE 2B. CE TO OUTPUT DELAY TIME

FIGURE 2C. CLOCK B TO OUTPUT DELAY TIME

NOTE:

FIGURE 2D. CLOCK A TO OUTPUT DELAY TIME

FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS

NOTE:

1. Output enabled when EN = high. Internal signal shown for refer-

ence only (see Figure 1).

FIGURE 3. TIMING DIAGRAM

FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER

N0 - N2

OUTPUT 0 - 7

CE

OUTPUT 0 - 7

MIN. CLOCK B

OUTPUT 0 - 7

CLOCK B

PULSE WIDTH

CLOCK A

OUTPUT 0 - 7

MIN. CLOCK A

PULSE WIDTH

(SEE NOTE 1)

TPA

TPB

CE

EN

OUTPUT

(NOTE 1)

A

B

C

CHIP ENABLE

CLK A

N0

N1

OUT 0

OUT 1

OUT 2

OUT 3

N2

CE

OUT 4

OUT 5

OUT 6

OUT 7

CLK B

CDP1853/3, CDP1853C/3