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CDP1853CD3 数据表(PDF) 3 Page - Intersil Corporation |
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CDP1853CD3 数据表(HTML) 3 Page - Intersil Corporation |
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3 / 7 page ![]() 4-42 Static Electrical Specifications PARAMETER SYMBOL CONDITIONS LIMITS UNITS VO (V) VIN (V) VDD (V) -55oC, +25oC +125oC MIN MAX MIN MAX Quiescent Device Current ISS (Note 1) - 0, 5 5 -50 - -100 - µA - 0, 10 10 -500 - -1000 - µA Output Low Drive (Sink) Current IOL 0.4 - 5 2.3 - 1.6 - mA 0.5 - 10 3.7 - 2.6 - mA Output High Drive (Source) Current IOH 4.6 - 5 - -1.7 - -1.2 mA 9.5 - 10 - -3.7 - -2.6 mA Output Voltage Low-Level VOL (Note 2) - 0, 5 5 - 0.1 - 0.2 V - 0, 10 10 - 0.1 - 0.2 V Output Voltage High-Level VOH (Note 2) - 0, 5 5 4.9 - 4.8 - V - 0, 10 10 9.9 - 9.8 - V Input Low Voltage VIL 0.8, 4.2 - 5 - 1.5 - 1.5 V 1, 9 - 10 - 3 - 3 V Input High Voltage VIH 0.8, 4.2 - 5 3.5 - 3.5 - V 1, 9 - 10 7 - 7 - V Input Leakage Low IIL - 0 5 -1 - -5 - µA - 0 10 -1 - -5 - µA Input Leakage High IIH -5 5-1-5 µA -10 10- 1 - 5 µA Input Capacitance CIN (Note 2) ---- 10 - 10 pF Output Capacitance COUT (Note 2) ---- 15 - 15 pF NOTES: 1. The CDP1853C meets all 5V static electrical characteristics of the CDP1853 except quiescent device current for which the limits are: ISS = -500µA at -55 oC and +25oC and I SS = -1000µA at +125 oC. 2. Guaranteed but not tested. Dynamic Electrical Specifications See Figure 2, CL = 100pF, tR, tF = 15ns PARAMETER SYMBOL VDD (V) LIMITS UNITS -55oC, +25oC +125oC MIN MAX MIN MAX Propagation Delay Time: tEOH 5 - 175 - 275 ns Chip Enable (CE) to Output High 10 - 90 - 150 ns CDP1853/3, CDP1853C/3 |
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