AD8351

Data Sheet

Rev. D | Page 14 of 19

Figure 40. ADC Driving Application Using Differential Input

The circuit of Figure 41 represents a single-ended input to

differential output configuration of the AD8351 driving the

the output voltages required for second-order cancellation by

the AD6645 and can be selected using a chart (see the Single-

Ended-to-Differential Operation section). The circuit depicted

in Figure 41 can provide SFDR performance of better than −90 dBc

with a 10 MHz input and −77 dBc with a 70 MHz input.

Figure 41. ADC Driving Application Using Single-Ended Input

ANALOG MULTIPLEXING

The AD8351 can be used as an analog multiplexer in applications

where it is desirable to select multiple high speed signals. The

isolation of each device when in a disabled state (PWUP pin

pulled low) is about 60 dBc for the maximum input level of

0.5 V p-p out to 100 MHz. The low output noise spectral density

allows for a simple implementation as depicted in Figure 42.

The PWUP interface can be easily driven using most standard

logic interfaces. By using an N-bit digital interface, up to N devices

can be controlled. Output loading effects and noise need to be

considered when using a large number of input signal paths. Each

disabled AD8351 presents approximately a 700 Ω load in parallel

with the 150 Ω output source impedance of the enabled device.

As the load increases due to the addition of N devices, the

distortion performance will degrade due to the heavier loading.

Distortion better than −70 dBc can be achieved with four devices

muxed into a 1 kΩ load for signal frequencies up to 70 MHz.

Figure 42. Using Several AD8351s to Form an N-Channel Analog MUX

I/O CAPACITIVE LOADING

Input or output direct capacitive loading greater than a few

picofarads can result in excessive peaking and/or oscillation

outside the pass band. This results from the package and bond

wire inductance resonating in parallel with the input/output

capacitance of the device and the associated coupling that results

internally through the ground inductance. For low resistive load

or source resistance, the effective Q is lower, and higher relative

capacitance termination or terminations can be allowed before

oscillation or excessive peaking occurs. These effects can be

capacitance, or series output resistors (ROP) for high load

capacitance. Generally less than 25 Ω is all that is required for I/O

capacitive loading greater than ~2 pF. The higher the C, the smaller

to reduce low gain in-band peaking, especially for light resistive

loads.

Used to Suppress Capacitive Loading Effects

BALANCE

50Ω

SOURCE

25Ω

25Ω

25Ω

25Ω

100nF

100nF

AD8351

INHI

INLO

OPHI

OPLO

VOCM

DIGITAL

OUT

AD6645

AIN

AIN VREF

SINGLE-

ENDED

50Ω

SOURCE

25Ω

R1

25Ω

25Ω

25Ω

100nF

100nF

AD8351

INHI

INLO

OPHI

OPLO

100nF

VOCM

DIGITAL

OUT

AD6645

AIN

AIN VREF

AD8351

INHI

RGP1

RGP2

INLO

SIGNAL

INPUT 1

SIGNAL

INPUT 2

SIGNAL

INPUT N

OPLO

OPHI

BIT 1

PWUP

AD8351

INHI

RGP1

RGP2

INLO

OPLO

OPHI

BIT 2

PWUP

AD8351

INHI

RGP1

RGP2

INLO

OPLO

OPHI

BIT N

PWUP

MUX

OUTPUT

LOAD

N-BIT

DIGITAL

INTERFACE

AD8351

1kΩ